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- Design enabled with C modeling,
VHDL/Verilog RTL, Architectural Coding.
- Completed cores for 0.18 micron technology - Gate level
net list / verified RTL code.
- EZW core using modified CDF (2,2) algorithm for 512 x 512 image DWT compression.
- 10 / 100 ETH MAC core, 12C core & FFT core suitable for 16 point, Radix 2 algorithm (integer version).
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